1. Field of the Invention
The invention relates to the fabricating of integrated circuits which employ double polycrystalline silicon layers.
2. Prior Art
In some MOS integrated circuits double polycrystalline silicon layers are employed for forming numerous circuit structures. Typically, a first or lower layer of polycrystalline silicon is insulated from a silicon substrate by an oxide layer with a second oxide layer insulating the lower silicon layer from an upper or second layer of polycrystalline silicon. These layers are fabricated into memory devices such as those employing floating gates, capacitors, interconnecting lines and others, with known photolithographic techniques. Such technology is presently employed in commercially available charged-coupled devices and programmable read-only memories.
In some of these double polycrystalline integrated circuit structures, it is desirable to have a member formed from the upper layer in alignment with a member formed from the lower layer. For example, where the upper and lower layers are used to define gates in field-effect devices, alignment between the gates may be important. With prior art fabrication processes, it is difficult to achieve such alignment. A prior art structure will be described in conjunction with FIG. 1 to illustrate one method by which the prior art indirectly solves this alignment problem.